1. Field of the Invention
The present invention relates to a thin film transistor and a manufacturing method thereof and, more particularly, to a thin film transistor having an inversely staggered configuration and a manufacturing method thereof.
2. Description of the Related Art
Liquid crystal display devices using thin film transistors (TFTs) as switching elements are widely proliferated in the marketplace, and as to a TFT using amorphous silicon (a-Si) for a semiconductor film, an inversely staggered configuration is widely adopted.
In a manufacturing method of a TFT which is formed by etching a channel (hereinafter referred to as a channel etch type TFT), a conductive layer to be formed as source and drain electrodes is etched by use of resist masks and is separated into a source electrode and a drain electrode. Further, n+ a-Si for forming an ohmic contact is etched to separate a source electrode contact and a drain electrode contact, and a TFT is formed. As to the manufacturing method of this channel etch type TFT, a manufacturing method using photomasks four times is adopted in order to reduce the number of process steps.
For instance, in Japanese Patent Laid-open No. 2000-164886 (hereinafter referred to as Patent Document 1), disclosed is a manufacturing method of a channel etch type TFT using photomasks four times as follows. FIG. 1A is a cross-sectional view showing the channel etch type TFT which is manufactured by the manufacturing method disclosed in Patent Document 1. With reference to FIG. 1A, the manufacturing method of the TFT is described. First, an electric conductor such as a metal is formed as a film on an insulating substrate 100. Patterning this conductor with lithography and etching technologies forms gate wiring and a gate electrode 101. Next, a gate insulating film 102 is formed on the insulating substrate 100, gate wiring and gate electrode 101. An a-Si film 103, an n+ a-Si film 104 and a metal film for source and drain electrodes are formed step by step on this gate insulating film 102. Reference numerals 105 and 106 denote the drain and source electrodes respectively, which are formed by patterning the metal film.
Next, by use of lithography technology, on the metal film for the source and drain electrodes, formed is a resist (not shown) which is thick in the areas forming source and drain electrodes and thin in the area between the areas in which the source and drain electrodes are formed. By using this resist as a mask, the metal film for the source and drain electrodes, the n+ a-Si film 104 and the a-Si film 103 are etched to perform a first patterning of the source electrode 106, drain electrode 105, a-Si film 103 and n+ a-Si film 104. When the n+ a-Si film 104 and a-Si film 103 are etched, at the same time the resist is etched so that the thin resist between the areas forming source and drain electrodes is removed thereby. The thick resist covering the forming areas of source electrode 106 and drain electrode 105 is etched such that the thickness thereof is reduced but the resist itself stays remained. By the use of this remaining resist as a mask, the metal film for the source and drain electrodes which is exposed between the forming areas of source electrode 106 and drain electrode 105 is etched. Further, the n+ a-Si film 104 between the forming areas of source electrode 106 and drain electrode 105 is etched, and a second patterning of the source electrode 106, drain electrode 105 and n+ a-Si film 104 is performed. Thereafter, the resist is removed.
Next, a passivation film 107 is formed all over the surface over the insulating substrate 100. Succeedingly, a contact hole 108 is opened in the passivation film 107 with lithography and etching technologies. Subsequently, on all over the passivation film 107 including the contact hole 108, a transparent conductive film is formed as a film. By using lithography and etching technologies, a pixel electrode 109 is formed by patterning this transparent conductive film. Then, the TFT is successfully formed.
Another example for a manufacturing method of a TFT in which four photomasks are used is disclosed in Japanese Patent Laid-open No. 2001-324725 (hereinafter referred to as Patent Document 2). FIG. 2 is a cross-sectional view showing a TFT manufactured by the manufacturing method described in Patent Document 2. In Patent Document 2 as in the Patent Document 1, a gate electrode 101 is formed on an insulating substrate 100. A gate insulating film 102 is formed on the insulating substrate 100 including the gate electrode. Next, a-Si film 103, n+ a-Si film 104 and a metal film for source and drain electrodes are deposited to form a multiple layered film on the gate insulating film 102. By using a resist as mask, the multiple layered film is etched to perform a first patterning of source electrode 106 and drain electrode 105, n+ a-Si film 104 and the a-Si film 103. Thereafter, the thickness of the resist is reduced by oxygen plasma so that the thin resist between the areas forming source and drain electrodes is removed thereby. Then, the TFT is formed through similar processes to Patent Document 1.
When the metal film for the source and drain electrodes, the n+ a-Si film 104 and the a-Si film 103 are etched by dry etching, in accordance with the manufacturing method of a TFT described in Patent Document 1, a difference in level is caused to be formed by the a-Si film 103, n+ a-Si film 104, drain electrode 105 and source electrode 106 as shown in FIG. 1A. A contact hole 108 is opened in a passivation film 107, and a pixel electrode 109 formed of a transparent conductive film such as indium tin oxide (ITO) film is formed. However, there has been a problem where the transparent conductive film of ITO film may be easily broken in the case of a large difference in level incurred.
Meanwhile, as described in Patent Document 1, when the etching of a metal film for the source and drain electrodes is performed by wet etching, the n+ a-Si film 104 and the source 106 and drain 105 electrodes can be formed as a step between them as shown in FIG. 1B. Therefore, as to the TFT in FIG. 1B, the problem of breaking wiring in the transparent conductive film described hereinbefore can be avoided.
As described in Patent Document 2, since the first patterning of the metal film for source and drain electrodes is performed by dry etching and the second patterning is performed by wet etching, a difference in level is formed by the a-Si film 103, n+ a-Si film 104, drain electrode 105 and source electrode 106 as shown in FIG. 2.
As commonly known, when light is irradiated from the transparent insulating substrate side of the TFT substrate, an off-current (leakage current) of the TFT increases due to the light reaching the a-Si film near the drain electrode without being blocked by the gate electrode. The light generates electron-hole pairs in the a-Si film and therefore a leakage current is caused to be generated by electrons and holes flowing attracted by an electric field. Deterioration of the picture quality in a liquid crystal display device is the consequence of the leakage current.
In a condition that the n+ a-Si film 104, and the source 106 and drain 105 electrodes are formed as a step between them as a configuration shown in FIG. 1B, the a-Si film 103 protrudes toward the outside of the gate electrode 101, drain electrode 105 and source electrode 106. On the surface of the protruded portion of the a-Si film 103, there exists the n+ a-Si film 104. Therefore, due to quick absorption of electrons into the n+ a-Si film 104 out of the electron and hole pairs generated by the light in the a-Si film 103, it is not possible to prevent the leakage current.
As in the configuration shown in FIG. 2, there exists the n+ a-Si film 104 on the surface of the a-Si film 103 protruded toward the outside from the gate electrode 101, and the source 106 and drain 105 electrodes. The area of n+ a-Si film 104 on the protruded a-Si film 103 is smaller than that in FIG. 1B. As a result, in FIG. 2, the amount of charges is reduced because of the recombination of electrons and holes on the back channel side, that is on the surface of the passivation film, among the electrons and holes generated by the light in the a-Si film 103. In other words, the leakage current decreases. Furthermore, when damage is caused by irradiation of ions on the exposed surface of the a-Si film 103 without having any n+ a-Si film 104 thereon, the mobility of electrons and holes can be reduced, and it is possible to increase recombination of electrons and holes. Thus, the leakage current can be suppressed.
However, when damage is caused by irradiation of ions on the exposed surface of the a-Si film 103 without having any n+ a-Si film 104 thereon, the a-Si film 103 which forms the channel area in the area above the gate electrode 101 also suffers similar damage. Thus, there exits a problem that a non-current is reduced if excess damage is caused to the exposed a-Si film 103 in order to achieve a reduced leakage current.